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tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 1 post office box 1443 ? houston, texas 772511443 organizatio n...16777216 by 4 bits single 3.3-v power supply ( 0.3-v tolerance) performance ranges: access access access edo time time time cycle t rac t cac t aa t hpc (max) (max) (max) (min) '46x409/p-40 40 ns 11 ns 20 ns 16 ns '46x409/p-50 50 ns 13 ns 25 ns 20 ns '46x409/p-60 60 ns 15 ns 30 ns 25 ns extended-data-out (edo) operation cas -before-ras (cbr) refresh long refresh period (see available options table) low-power, self-refresh version (tms46x409p) 3-state unlatched output all inputs / outputs and clocks are low-voltage ttl (lvttl) compatible high-reliability plastic 32-lead 400-mil-wide thin small-outline (tsop) package (dgc suffix) operating free-air temperature range 0 c to 70 c available options device self-refresh battery backup ras -only refresh cycles cbr refresh cycles tms464409 e 8 192 in 64 ms 4 096 in 64 ms TMS464409P yes 8 192 in 128 ms 4 096 in 128 ms tms465409 e 4 096 in 64 ms 4 096 in 64 ms tms465409p yes 4 096 in 128 ms 4 096 in 128 ms description the tms464409 and tms465409 series are low-voltage, 67 108 864-bit dynamic random-access memories (drams), organized as 16 777 216 words of 4 bits each. the TMS464409P and tms465409p series are high-speed, low-voltage, low-power, self-refresh, 67 108 864-bit drams, organized as 16 777 216 words of 4 bits each. both sets of devices employ state-of-the-art technology for high performance, reliability, and low power. these devices feature maximum ras access times of 40, 50, and 60 ns. all inputs and outputs, including clocks, are compatible with lvttl. all addresses and data-in lines are latched on chip to simplify system design. data out is unlatched to allow greater system flexibility. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. product preview dgc package ( top view ) pin nomenclature a0 a12 address inputs cas column-address strobe dq1 dq4 data in / data out nc no internal connection oe output enable ras row-address strobe w write enable v cc 3.3-v supply v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc dq1 dq2 nc nc nc nc w ras a0 a1 a2 a3 a4 a5 v cc v ss dq4 dq3 nc nc nc cas oe a12 2 a11 a10 a9 a8 a7 a6 v ss 2 a12 is nc for tms465409 and tms465409p. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. copyright ? 1997, texas instruments incorporated
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 2 post office box 1443 ? houston, texas 772511443 description (continued) the tms46x409 and tms46x409p series are offered in a 400-mil, 32-lead plastic surface mount tsop package (dgc suffix). this package is designed for operation from 0 c to 70 c. logic symbol (tms464409 and TMS464409P) 2 a0 a1 a2 a3 a4 a5 a6 a7 10 11 12 13 14 15 18 19 dq2 dq3 dq4 dq1 ras cas w oe 3 30 31 9 26 8 2 25 ram 16m 4 20d11/21d0 c20[row] g23/[refresh row] 24[pwr dwn] c21[col] g24 & 23c22 23,21d 24 ,25en a,z26 a8 20 a9 21 g25 a,22d ? 26 a 0 16777216 a10 22 a11 23 a12 24 20d23/ 20d20/21d9 20d21/21d10 20d22/ 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 3 post office box 1443 ? houston, texas 772511443 logic symbol (tms465409 and tms465409p) 2 a0 a1 a2 a3 a4 a5 a6 a7 10 11 12 13 14 15 18 19 dq2 dq3 dq4 dq1 ras cas w oe 3 30 31 9 26 8 2 25 ram 16m 4 20d12/21d0 c20[row] g23/[refresh row] 24[pwr dwn] c21[col] g24 & 23c22 23,21d 24 ,25en a,z26 a8 20 a9 21 g25 a,22d ? 26 a 0 16777216 a10 22 a11 23 20d22/21d10 20d23/21d11 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 4 post office box 1443 ? houston, texas 772511443 functional block diagram tms464409, TMS464409P r o w d e c o d e a0 a1 a10 timing and control column- address buffers row- address buffers i/o buffers data- in reg. data- out reg. column decode sense amplifiers 32 512k array 512k array 512k array ras cas w dq1 dq4 4 4 oe 11 13 12 4 4 2 a11, a12 tms465409, tms465409p a0 a1 a11 16 timing and control column- address buffers row- address buffers i/o buffers data- in reg. data- out reg. column decode sense amplifiers r o w d e c o d e 16 512k array 512k array 512k array 512k array 512k array 512k array ras cas w dq1 dq4 4 4 oe 12 12 11 4 4 product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 5 post office box 1443 ? houston, texas 772511443 operation extended data out extended data out (edo) allows data output rates up to 66 mhz for 40-ns devices. when keeping the same row address while selecting random column addresses, the time for row-address setup and hold and for address multiplex is eliminated. the maximum number of columns that can be accessed is determined by t rasp , the maximum ras low time. extended data out does not place the data in / data out pins (dq pins) into the high-impedance state with the rising edge of cas during ras low. the output remains valid for the system to latch the data. after cas goes high, the dram decodes the next address. oe and w can control the output impedance. descriptions of oe and w further explain edo operation benefit. address: a0 a11 ( tms465409/p) and a0 a12 (tms464409/p) twenty-four address bits are required to decode each one of 16 777 216 storage cell locations. for the tms465409 and tms465409p,12 row-address bits are set up on a0 through a11 and latched onto the chip by the row-address strobe (ras ). twelve column-address bits are set up on a0 through a11. for the tms464409 and TMS464409P, 13 row-address bits are set up on inputs a0 through a12 and latched onto the chip by ras . eleven column-address bits are set up on a0 through a10. all addresses must be stable on or before the falling edge of ras and cas . ras is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. cas is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. output enable (oe ) oe controls the impedance of the output buffers. while cas and ras are low and w is high, oe can be brought low or high and the dqs transition between valid data and high impedance (see figure 8). there are two methods for placing the dqs into the high-impedance state and maintaining that state during cas high time. the first method is to transition oe high before cas transitions high and keep oe high for t cho (hold time, oe from cas ) past the cas transition. this disables the dqs and they remain disabled, regardless of oe , until cas falls again. the second method is to have oe low as cas transitions high. then oe can pulse high for a minimum of t oep (precharge time, oe ) anytime during cas high time, disabling the dqs regardless of further transitions on oe until cas falls again (see figure 8). write enable ( w ) the read or write mode is selected through w . a logic high on w selects the read mode, and a logic low selects the write mode. the data inputs are disabled when the read mode is selected. when w goes low prior to cas (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with oe grounded. if w goes low in an extended-data-out read cycle, the dqs are disabled so long as cas is high (see figure 9). data in / data out (dq1 dq4) data is written during a write or read-modify-write cycle. depending on the mode of operation, the later falling edge of cas or w strobes data into the on-chip data latch with setup and hold times referenced to the later edge. the dqs drive valid data after all access times are met and remain valid except in cases described in the w and oe descriptions. ras -only refresh a refresh operation must be performed at least once every 64 ms (128 ms for tms46x409p) to retain data by strobing each of the 4096 rows for tms465409/p or 8192 rows for tms464409/p. a normal read or write cycle refreshes all bits in each row that is selected. a ras -only operation can be used by holding cas at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. externally generated addresses must be used for a ras -only refresh. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 6 post office box 1443 ? houston, texas 772511443 hidden refresh a hidden refresh can be performed while maintaining valid data at the output pin. this is accomplished by holding cas at v il after a read operation and cycling ras after a specified precharge period, similar to a ras -only refresh cycle. the external address is ignored, and the refresh address is generated internally. cas -before-ras ( cbr) refresh cbr refresh is performed by bringing cas low earlier than ras (see parameter t csr ) and holding it low after ras falls (see parameter t chr ). for successive cbr refresh cycles, cas can remain low while cycling ras . the external address is ignored, and the refresh address is generated internally. battery-backup refresh a low-power battery-backup refresh mode that requires less than 250 a of refresh current is available on the TMS464409P and tms465409p. data integrity is maintained using cbr refresh with a period of 31.25 s while holding ras low for less than 300 ns. to minimize current consumption, all input levels must be at lvcmos levels (v il < 0.2 v, v ih >v cc 0.2 v). self-refresh (tms46x409p) the self-refresh mode is entered by dropping cas low prior to ras going low. then cas and ras are both held low for a minimum of 100 s. the chip is then refreshed internally by an on-board oscillator. no external address is required because the cbr counter is used to keep track of the address. to exit the self-refresh mode, both ras and cas are brought high to satisfy t chs . upon exiting self-refresh mode, a burst refresh (refreshes a full set of row addresses) must be executed before continuing with normal operation. the burst refresh ensures the dram is fully refreshed. power up to achieve proper device operation, an initial pause of 200 m s followed by a minimum of eight initialization cycles is required after power up to the full v cc level. these eight initialization cycles must include at least one refresh ( ras -only or cbr ) cycle. test mode the test mode (see figure 1) is initiated with a cbr-refresh cycle while simultaneously holding the w input low. the entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. while in the test mode, any data sequence can be performed. the device exits test mode if a cbr refresh cycle with w held high or a ras -only refresh cycle is performed. in the test mode, the device is configured as 1024k bits 4 bits for each dq. each dq pin has a separate 4-bit parallel read and write data bus that ignores column addresses a0 and a1. during a read cycle, the four internal bits are compared for each dq pin. if the four bits agree, dq goes high; if not, dq goes low. during a write cycle, the data states of all four dqs must be the same to ensure proper function of the test mode. test time is reduced by a factor of four for this series. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 7 post office box 1443 ? houston, texas 772511443 test mode (continued) test mode cycle entry cycle exit cycle normal mode ras cas w note a: the states of w , data in, and address are defined by the type of cycle used during test mode. figure 1. test-mode cycle product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 8 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range on v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range on any pin (see note 1) 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . short-circuit output current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 v cc + 0.3 v v il low-level input voltage (see note 2) 0.3 0.8 v t a operating free-air temperature 0 70 c note 2: the algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic volt age levels only. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 9 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) tms464409/p parameter test conditions 2 '464409-40 '464409p-40 '464409-50 '464409p-50 '464409-60 '464409p-60 unit min max min max min max v oh high-level i oh = 2 ma lvttl 2.4 2.4 2.4 v v oh g output voltage i oh = 100 m a lvcmos v cc 0.2 v cc 0.2 v cc 0.2 v v ol low-level i ol = 2 ma lvttl 0.4 0.4 0.4 v v ol output voltage i ol = 100 m a lvcmos 0.2 0.2 0.2 v i i input current (leakage) v cc = 3.6 v, v i = 0 v to 3.9 v, all others = 0 v to v cc 10 10 10 m a i o output current (leakage) v cc = 3.6 v, v o = 0 v to v cc , cas high 10 10 10 m a i cc1 3 average read- or write-cycle current v cc = 3.6 v, minimum cycle 125 100 90 ma average after one memory cycle, ras and cas high, v ih = 2 v (lvttl) 1 1 1 ma i cc2 a v erage standby current after one memory cycle, ras and cas hi g h, '464409 500 500 500 m a g, v ih = v cc 0.2 v (lvcmos) '464409p 150 150 150 m a i cc3 average ras -only refresh current v cc = 3.6 v, minimum cycle, ras cycling, cas high (ras only) 125 100 90 ma i cc4 3? average edo current v cc = 3.6 v, t pc = minimum, ras low, cas cycling 140 110 90 ma i cc5 average cbr refresh current v cc = 3.6 v, minimum cycle, ras low after cas low 160 130 110 ma i cc6 # average self-refresh current cas < 0.2 v, ras < 0.2 v, measured after t rass minimum 300 300 300 m a i cc10 # average battery-backup operating current, cbr only t ras 300 ns, t rc = 31.25 s v cc 0.2 v v ih 3.9 v, 0 v v il 0.2 v, w and oe = v ih , address and data stable 400 400 400 m a 2 for conditions shown as min / max, use the appropriate value specified in the timing requirements. 3 measured with outputs open measured with a maximum of one address change while ras = v il ? measured with a maximum of one address change per edo cycle, t hpc # for TMS464409P only product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 10 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tms465409/p parameter test conditions 2 '465409-40 '465409p-40 '465409-50 '465409p-50 '465409-60 '465409p-60 unit min max min max min max v oh high-level i oh = 2 ma lvttl 2.4 2.4 2.4 v v oh g output voltage i oh = 100 m a lvcmos v cc 0.2 v cc 0.2 v cc 0.2 v v ol low-level i ol = 2 ma lvttl 0.4 0.4 0.4 v v ol output voltage i ol = 100 m a lvcmos 0.2 0.2 0.2 v i i input current (leakage) v cc = 3.6 v, v i = 0 v to 3.9 v, all others = 0 v to v cc 10 10 10 m a i o output current (leakage) v cc = 3.6 v, v o = 0 v to v cc , cas high 10 10 10 m a i cc1 3 average read- or write-cycle current v cc = 3.6 v, minimum cycle 160 130 110 ma average after one memory cycle, ras and cas high, v ih = 2 v (lvttl) 1 1 1 ma i cc2 a v erage standby current after one memory cycle, ras and cas hi g h, '465409 500 500 500 m a g, v ih = v cc 0.2 v (lvcmos) '465409p 150 150 150 m a i cc3 average ras -only refresh current v cc = 3.6 v, minimum cycle, ras cycling, cas high (ras only) 160 130 110 ma i cc4 3? average edo current v cc = 3.6 v, t pc = minimum, ras low, cas cycling 150 120 100 ma i cc5 average cbr refresh current v cc = 3.6 v, minimum cycle, ras low after cas low 160 130 110 ma i cc6 # average self-refresh current cas < 0.2 v, ras < 0.2 v, measured after t rass minimum 300 300 300 m a i cc10 # average battery-backup operating current, cbr only t ras 300 ns, t rc = 31.25 s v cc 0.2 v v ih 3.9 v, 0 v v il 0.2 v, w and oe = v ih , address and data stable 400 400 400 m a 2 for conditions shown as min / max, use the appropriate value specified in the timing requirements. 3 measured with outputs open measured with a maximum of one address change while ras = v il ? measured with a maximum of one address change per edo cycle, t hpc # for tms465409p only product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 11 post office box 1443 ? houston, texas 772511443 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 mhz (see note 3) parameter min max unit c i(a) input capacitance, a0 a12 2 5 pf c i(oe) input capacitance, oe 7 pf c i(rc) input capacitance, cas and ras 7 pf c i(w) input capacitance, w 7 pf c o output capacitance 3 7 pf 2 a12 is nc (no internal connection) for tms465409 and tms465409p. 3 cas and oe = v ih to disable outputs note 3: v cc = 3.3 v 10%, and the bias on pins under test is 0 v. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see note 4) parameter '46x409-40 '46x409p-40 '46x409-50 '46x409p-50 '46x409-60 '46x409p-60 unit min max min max min max t aa access time from column address (see note 5) 20 25 30 ns t cac access time from cas (see note 5) 11 13 15 ns t cpa access time from cas precharge (see note 5) 22 28 35 ns t rac access time from ras (see note 5) 40 50 60 ns t oea access time from oe (see note 5) 11 13 15 ns t clz delay time, cas to output in low impedance 0 0 0 ns t rez output buffer turn off delay from ras (see note 6) 3 11 3 13 3 15 ns t cez output buffer turn off delay from cas (see note 6) 3 11 3 13 3 15 ns t oez output buffer turn off delay from oe (see note 6) 3 11 3 13 3 15 ns t wez output buffer turn off delay from w (see note 6) 3 11 3 13 3 15 ns notes: 4. with ac parameters, it is assumed that t t = 2 ns. 5. access times are measured with output reference levels of v oh = 2 v and v ol = 0.8 v. 6. the maximum values of t rez , t cez , t oez , and t wez are specified when the output is no longer driven. data in should not be driven until one of the applicable maximum specs is satisfied. edo timing requirements over recommended ranges of supply voltage and operating free-air temperature (see note 4) '46x409-40 '46x409p-40 '46x409-50 '46x409p-50 '46x409-60 '46x409p-60 unit min max min max min max t hpc cycle time, edo page mode, read-write 16 20 25 ns t prwc cycle time, edo read-write 47 57 68 ns t csh delay time, ras active to cas precharge 32 40 48 ns t cho hold time, oe from cas 5 5 5 ns t doh hold time, output from cas 5 5 5 ns t cas pulse duration, cas active (see note 7) 6 10 000 8 10 000 10 10 000 ns t wpe pulse duration, w active (output disable only) 5 5 5 ns t och setup time, oe before cas 5 5 5 ns t cp pulse duration, cas precharge 6 8 10 ns t oep precharge time, oe 5 5 5 ns notes: 4. with ac parameters, it is assumed that t t = 2 ns. 7. in a read-write cycle, t cwd and t cwl must be observed. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 12 post office box 1443 ? houston, texas 772511443 timing requirements (see note 4) '46x409-40 '46x409p-40 '46x409-50 '46x409p-50 '46x409-60 '46x409p-60 unit min max min max min max t rc cycle time, random read or write 69 84 104 ns t rwc cycle time, read-write 92 111 135 ns t rasp pulse duration, ras active, fast page mode (see note 8) 40 100 000 50 100 000 60 100 000 ns t ras pulse duration, ras active, non-page mode (see note 8) 40 10 000 50 10 000 60 10 000 ns t rp pulse duration, ras precharge 25 30 40 ns t wp pulse duration, write command 6 8 10 ns t rass pulse duration, ras active, self refresh (see note 9) 100 100 100 s t rps pulse duration, ras precharge after self refresh 70 90 110 ns t asc setup time, column address 0 0 0 ns t asr setup time, row address 0 0 0 ns t ds setup time, data in (see note 9) 0 0 0 ns t rcs setup time, read command 0 0 0 ns t cwl setup time, write command before cas precharge 6 8 10 ns t rwl setup time, write command before ras precharge 6 8 10 ns t wcs setup time, write command before cas active (early-write only) 0 0 0 ns t wrp setup time, w high before ras low (cbr refresh only) 5 5 5 ns t wts setup time, w low before ras low (test mode only) 5 5 5 ns t csr setup time, cas referenced to ras ( cbr refresh only ) 5 5 5 ns t cah hold time, column address 6 8 10 ns t dh hold time, data in (see note 10) 6 8 10 ns t rah hold time, row address 6 8 10 ns t rch hold time, read command referenced to cas (see note 11) 0 0 0 ns t rrh hold time, read command referenced to ras (see note 11) 0 0 0 ns t wch hold time, write command during cas active ( early-write only ) 6 8 10 ns t roh hold time, ras referenced to oe 6 8 10 ns t wrh hold time, w high after ras low (cbr refresh) 6 8 10 ns t wth hold time, w low after ras low (test mode only) 6 8 10 ns t chr hold time, cas referenced to ras (cbr refresh only ) 6 8 10 ns t oeh hold time, oe command 11 13 15 ns t chs hold time, cas active after ras precharge (self-refresh) 50 50 50 ns t rhcp hold time, ras active from cas precharge 22 28 35 ns notes: 4. with ac parameters, it is assumed that t t = 2 ns. 8. in a read-write cycle, t rwd and t rwl must be observed. 9. during the period of 10 s t rass 100 s, the device is in transition state from normal operation mode to self-refresh mode. 10. referenced to the later of cas or w in write operations 11. either t rrh or t rch must be satisfied for a read cycle. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 13 post office box 1443 ? houston, texas 772511443 timing requirements (see note 4) (continued) '46x409-40 '46x409p-40 '46x409-50 '46x409p-50 '46x409-60 '46x409p-60 unit min max min max min max t awd delay time, column address to write command ( read-write only ) 35 42 49 ns t cpw delay time, w low after xcas precharge (read-write only) 37 45 54 ns t crp delay time, cas precharge to ras 5 5 5 ns t cwd delay time, cas to write command ( read-write only ) 26 30 34 ns t oed delay time, oe to data in 11 13 15 ns t rad delay time, ras to column address (see note 12) 8 20 10 25 12 30 ns t ral delay time, column address to ras precharge 20 25 30 ns t cal delay time, column address to cas precharge 12 15 18 ns t rcd delay time, ras to cas ( see note 12) 10 29 12 37 14 45 ns t rpc delay time, ras precharge to cas 5 5 5 ns t rsh delay time, cas active to ras precharge 6 8 10 ns t rwd delay time, ras to write command (read-write only) 55 67 79 ns t taa access time from address (test mode) 25 30 35 ns t tcpa access time, from column precharge (test mode) 30 35 40 ns t trac access time, from ras (test mode) 45 55 65 ns t t transition time 1 50 1 50 1 50 ns t ref refresh time interval '46x409 64 64 64 ms t ref refresh time interval '46x409p 128 128 128 ms notes: 4. with ac parameters, it is assumed that t t = 2 ns. 12. the maximum value is specified only to ensure access time. product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 14 post office box 1443 ? houston, texas 772511443 parameter measurement information 1.4 v 3.3 v c l = 100 pf (see note a) output under test output under test c l = 100 pf (see note a) (b) alternate load circuit (a) load circuit note a: c l includes probe and fixture capacitance. 500 1178 868 figure 2. load circuits for timing parameters product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 15 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 t rc row column don't care don't care don't care don't care don't care valid data out t ras t rp t csh t t t rcd t rsh t crp t cas t rad t asc t ral t asr t rcs t cah t rrh t rch t cac t cez t aa t clz t rac t oea t roh t oez t cp see note a hi-z t rah t rez t wez t wpe t cal note a: output can go from the high-impedance state to an invalid-data state prior to the specified access time. figure 3. read-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 16 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 t rc row column don't care don't care don't care don't care valid data don't care t rp t ras t rsh t crp t cas t rcd t t t csh t asc t asr t ral t cah t cp t rad t cwl t rwl t wch t dh t ds t rah t wcs t cal figure 4. early-write-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 17 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 t rc row column don't care don't care don't care don't care don't care t ras t rp t rsh t crp t cas t rcd t csh t t t asr t rah t asc t ral t cah t rad t cwl t rwl t wp t clz t dh t oed t oeh t cp t ds don't care invalid data out valid data in t cal figure 5. write-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 18 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 t rwc row column don't care don't care don't care data out don't care don't care data in t ras t rcd t t t cas t rp t crp t cp t t t cah t asc t rah t asr t rad t rcs t rwd t rwl t wp t awd t cwd t cac t ds t dh t aa t clz t rac t oea t oez t oed t oeh see note a t cwl hi-z note a: output can go from the high-impedance state to an invalid-data state prior to the specified access time. figure 6. read-write-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 19 post office box 1443 ? houston, texas 772511443 parameter measurement information data #3 data #2 data #1 column #3 column #2 column #1 row dq1 dq4 w oe address cas ras t cez t clz t asc t crp t cas t rch t doh t cac t rad t cah t rah t asr t cp t t t rp t rcs t rac t aa t aa t cpa t rez t rrh t oea t ral t rsh t hpc t csh t rcd t rasp t cal t cac t rhcp (see note a) (see note c (see note b) notes: a. output can go from the high-impedance state to an invalid-data state prior to the specified access time. b. access time is t cpa -, t aa -, or t cac -dependent. c. output is turned off by t cez if ras goes high during cas low. figure 7. edo read cycle product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 20 post office box 1443 ? houston, texas 772511443 parameter measurement information t oez t cac t oea t oep t cho t oep t cah t asc t rah t asr t aa t cac t clz t doh t rez t rch t rrh t rad t rsh t rp dq1 dq4 w oe address cas ras t cpa t aa t rac t rcs t oea t hpc t csh t rasp t ral row column #1 column #2 column #3 data #1 data #1 data #2 data #3 t cas t cp t oez t cez t och t rhcp t cal (see note a) note a: output is turned off by t cez if ras goes high during cas low. figure 8. edo read-cycle with oe control product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 21 post office box 1443 ? houston, texas 772511443 parameter measurement information column #3 column #2 column #1 row data #3 data #2 data #1 dq1 dq4 w oe address cas ras t crp t rsh t asr t rah t asc t cah t rrh t rch t cac t wpe t clz t cac t cez t rez t wez t cas t cac t aa t cpa t aa t cpa t aa t rac t rcs t oea t rad t rasp t hpc t csh t cp t rp t cal t rhcp t doh t ral figure 9. edo read-cycle with w control product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 22 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 row column don't care t rp data in don't care don't care don't care don't care column t csh t hpc t rsh t cas t rcd t asc t rah t cah t cp t asr t wch t cwl t rwl t dh t ds t ral t crp t cwl t rad t cal don't care data in t rasp t rhcp t wcs note a: a read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specificati ons are not violated. figure 10. edo early-write-cycle timing (see note a) product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 23 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 row column don't care don't care valid in t rp valid data in don't care don't care don't care don't care column t rasp t csh t hpc t crp t rsh t cas t rcd t asc t rah t cah t cp t asr t rad t cwl t wp t oeh t oeh t oed t ral t cal t rhcp t ds t dh don't care t clz don't care t cwl t rwl invalid data out note a: a read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specificati ons are not violated. figure 11. edo write-cycle timing (see note a) product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 24 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w oe dq1 dq4 row column 1 don't care valid in 2 column 2 t rasp valid in 1 t rp t csh t prwc t rcd t cp t crp t rsh t asc t cah t rad t asr t cwd t rah t awd t cwl t rwl t wp t rwd t cpa t oeh t dh t ds t aa t rcs t rac t cac t clz t oea t oez t oeh t oed t cas valid out 2 (see note a) valid out 1 t cal t ral t cpw notes: a. output can go from the high-impedance state to an invalid-data state prior to the specified access time. b. a read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not v iolated. figure 12. edo read-write-cycle timing (see note b) product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 25 post office box 1443 ? houston, texas 772511443 parameter measurement information t rc t ras t rp t t t asr t rah t crp t rpc ras cas address w oe don't care don't care row row don't care don't care hi z don't care figure 13. ras -only refresh-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 26 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas w address oe dq1 dq4 t rc don't care don't care hi-z t ras t rp t csr t rpc t t t chr t wrp t wrh figure 14. automatic-cbr-refresh-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 27 post office box 1443 ? houston, texas 772511443 parameter measurement information t rass t csr t rpc ras cas address t rps t cp don't care w don't care oe don't care dq1 dq4 t chs hi-z t wrp t wrh figure 15. self-refresh-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 28 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address row col don't care w oe dq1 dq4 valid data out t ras t rp t rp t ras t cas t cah t asc t rah t asr t rcs t wrp t wrh t wrh t wrp t cez t clz t oea t oez t chr refresh cycle refresh cycle memory cycle t wrh t wrp t rez t wez t rrh t rac t cac t aa figure 16. hidden-refresh-cycle (read) timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 29 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas address w dq1 dq4 oe row col don't care valid data don't care don't care refresh cycle memory cycle refresh cycle t ras t rp t ras t rp t chr t cas t cah t asc t rah t asr t wcs t wp t wrp t wrh t dh t ds t wch figure 17. hidden-refresh-cycle (write) timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 30 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas w address oe dq1 dq4 t rc don't care don't care hi-z t ras t rp t csr t rpc t t t chr t wts t wth don't care figure 18. test-mode-entry-cycle timing ras cas address w dq1 dq4 t rp t rc t ras t rpc t csr t t t chr t wrp t wrh don't care don't care don't care t cez hi-z don't care t rez figure 19. test-mode-exit-cycle cbr-refresh-cycle timing product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 31 post office box 1443 ? houston, texas 772511443 mechanical data dgc (r-pdso-g32) plastic small-outline package 4040260-3 / b 02/95 17 0.020 (0,50) 0.012 (0,30) 0.000 (0,00) min 0.047 (1,20) max 1 32 0.829 (21,05) 0.821 (20,85) 0.016 (0,40) seating plane 0.006 (0,15) nom 0.471 (11,96) 0.455 (11,56) 0.396 (10,06) 16 0.404 (10,26) gage plane 0.010 (0,25) 0.024 (0,60) 0.004 (0,10) m 0.008 (0,20) 0.050 (1,27) 0 5 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. device symbolization (tms464409 illustrated) speed ( - 40, - 50, - 60) package code low-power / self-refresh designator (blank or p) -ss tms464409 dgc assembly site code lot traceability code year code die revision code wafer fab code p llll y a w m month code ti product preview
tms464409, TMS464409P, tms465409, tms465409p 16 777 216 by 4-bit extended data out dynamic random-access memories smks895a may 1997 revised october 1997 32 post office box 1443 ? houston, texas 772511443 product preview
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